1. Field of the Invention
The present invention relates to a method of forming a deep trench capacitor buried plate, and more particularly, to a method for preventing the doped ions from diffusing to the collar region and for avoiding increasing the critical dimension of the deep trench.
2. Description of the Prior Art
As very large scale integration (VLSI) technologies develop, the dimension of the semiconductor elements becomes more and more tiny than before. However, the short channel effect is an obstacle to increase the semiconductor element integration. Before now, some methods are proposed to prevent the short channel effect, such as reducing the thickness of the gate oxide layer or increasing the doped concentration. But these methods lead to some disadvantages, such as lower reliability and lower rate. As a result, a vertical transistor design, which is able to increase the integration, is highly evaluated. Take dynamic random access memory (DRAM) as an example; a deep trench memory integrates the storage capacitor, or even the gate, source, and drain of the transistor into the trench, such that the integration is effectively increased.
Refer to FIG. 1 to FIG. 4, which are schematic diagrams illustrating a method of forming a deep trench capacitor buried plate according to the prior art. As shown in FIG. 1, first a substrate 10 is provided, and a pad oxide layer 12 and a pad nitride layer 14 are deposited on the substrate 10 in turn. Then a deep trench 16 is formed in the substrate 10.
As shown in FIG. 2, an arsenic silicate glass (ASG) layer 18 is deposited on the inner wall of the deep trench 16, and a sacrificial layer (not shown in FIG. 2) is deposited to fill up the deep trench 16. Then the sacrificial layer (not shown) is etched back to expose a portion of the arsenic silicate glass layer 18. Afterward, an etching process is performed to remove the exposed arsenic silicate glass layer 18 such that a collar region 20 is formed in the deep trench 16. Finally another etching process is performed to remove the remaining sacrificial layer (not shown).
As shown in FIG. 3, a deposition process is performed by use of TEOS (tetra-ethyl-ortho-silicate) as a precursor to form a TEOS layer 22 on the inner wall of the deep trench 16. Then a thermal process is performed to diffuse the arsenic ions of the arsenic silicate glass layer 18 into the substrate 10, such that a doped region 24, serving as a buried plate, is formed.
Finally as shown in FIG. 4, an etching process is performed to remove the TEOS layer 22 and the arsenic silicate glass layer 18 as well to carry out the deep trench capacitor buried plate.
As has been pointed out, the prior art method of forming the deep trench capacitor buried plate utilizes a TEOS layer as a barrier layer, and a thermal process is performed to diffuse the arsenic ions into the substrate such that a doped region, serving as a buried plate, is formed. However, since TEOS has poor step coverage ability, a void will easily occur in the opening of the deep trench as the dimension decreases. In addition, as shown in FIG. 3, the TEOS layer 22 does not afford good results as a barrier layer, thus the arsenic ions will easily pass through the TEOS layer 22 and diffuse into the collar region 22. The arsenic ions in the collar region 22 will cause current leakages of the capacitor.
Moreover, the pad oxide layer and the TEOS layer are both composed of silicon oxide, as a consequence when an etching process is performed to remove the TEOS layer, some pad oxide layer will be removed as well. The removal of the pad oxide layer would increase the critical dimension of the deep trench, and further lead to a short circuit between neighboring deep trenches.